Search - fpga dds VHDL

[VHDL-FPGA-Verilog] FPGA_SUM99_VHDL_SOURCE

Description: 基于FPGA的直接数字合成器的设计与分析的代码程序,代码格式为VHDL-FPGA-based Direct Digital Synthesis Design and Analysis of the code procedures for VHDL code format
Platform: | Size: 5120 | Author: 莫汉伟 | Hits:

[Communication] Project1-DDS

Description: 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
Platform: | Size: 8192 | Author: lf | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 用51和 FPGA实现的 DDS的程序-FPGA with 51 and realize the process of DDS
Platform: | Size: 5120 | Author: 胡玉贵 | Hits:

[Communication-Mobile] DDFS_PLL_10DA_with51

Description: FPGA下的DDS程序的编写,VHDL语言,-FPGA under DDS preparation procedures, VHDL language,
Platform: | Size: 627712 | Author: huang | Hits:

[VHDL-FPGA-Verilog] msp430_jtag_nios

Description: 将msp430与使用nios的fpga相连，将fpga作为msp430的jtag使用。其中用到了nios内的多种接口以及dma操作-The MSP430 with the use of the Nios FPGA connected to the FPGA as the MSP430 JTAG to use. Which used the Nios multiple interfaces and dma operation
Platform: | Size: 56320 | Author: danielmu | Hits:

[VHDL-FPGA-Verilog] dds

Description: DDS正弦信号发生器频率和相位连续可调。频率最大2M
Platform: | Size: 3072 | Author: dsf | Hits:

[VHDL-FPGA-Verilog] dds

Description: 利用fpga实现的DDS，可输出正弦波，输出频率可调-FPGA realization of the use of DDS, sine wave output, output frequency adjustable
Platform: | Size: 468992 | Author: qlg | Hits:

[Wavelet] DDS

Description: 利用EDA技术和FPGA在UP3开发板上实现直接数字频率综合器的设计。实验中加入了相位控制字PWORD，用以控制相位偏移量的前四位，将相位偏移量加到ROM地址总线上，从而引起从ROM中取得的正弦信号的偏移，实现移相信号发生器的移相功能。实验中还加入了LCD显示功能，通过LCD显示模块器件，用LCD显示正弦信号的频率，所显示的频率也是由频率字控制的。LCD的驱动原理同上次实验。-The use of EDA technology and FPGA development in the UP3 board direct digital frequency synthesizer design. Experiment by adding a phase control word PWORD, to control the phase offset of the top four will be added to the phase offset ROM address bus, thereby causing ROM obtained from the sinusoidal signal offset, shifted believe realize its phase-shifting function generator. Experiments have also joined the LCD display, LCD display module through the device, with LCD display the frequency of sinusoidal signal, as shown by the frequency of word frequency control. LCD driving principles with the previous experiment.
Platform: | Size: 1225728 | Author: Emma | Hits:

[VHDL-FPGA-Verilog] vhdl-dds

Description: fpga 控制dds 程序。希望对各位有用-dds FPGA control procedures. Members wish to be useful
Platform: | Size: 88064 | Author: martin | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于VHDL+FPGA的DDS信号发生设计，已经通过调式-Based on VHDL+ FPGA design of the DDS signal has been through mode
Platform: | Size: 560128 | Author: 陈阳 | Hits:

[Software Engineering] DDS

Description: 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
Platform: | Size: 558080 | Author: 毛华站 | Hits:

[Software Engineering] dds

Description: 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
Platform: | Size: 1695744 | Author: 姜兆刚 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA，vhdl语言的学习资料； FPGA的简单设计 dds的设计-FPGA, vhdl language learning materials FPGA design of a simple design dds
Platform: | Size: 2098176 | Author: wade | Hits:

[Books] dds

Description: FPGA实现DDS，f=90kHZ~5MHZ范围-FPGA realization of DDS, f = 90kHZ ~ 5MHZ the scope of
Platform: | Size: 1442816 | Author: 王勤 | Hits:

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[VHDL-FPGA-Verilog] FPGA_SUM99_VHDL_SOURCE

[Communication] Project1-DDS

[VHDL-FPGA-Verilog] DDS

[Communication-Mobile] DDFS_PLL_10DA_with51

[VHDL-FPGA-Verilog] msp430_jtag_nios

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds

[Wavelet] DDS

[VHDL-FPGA-Verilog] vhdl-dds

[VHDL-FPGA-Verilog] dds

[Software Engineering] DDS

[Software Engineering] dds

[VHDL-FPGA-Verilog] FPGA

[Books] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] dds

[Program doc] FPGA-DDS-FM

[VHDL-FPGA-Verilog] FPGA-DDS

[VHDL-FPGA-Verilog] DDS-FPGA

[VHDL-FPGA-Verilog] DDS

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